Execution Order for Logic Programs

Each part of a Logic program is executed in a sequence that is referred to as the "execution order". The way in which ClearSCADA determines the execution order varies according to the type of Logic program:

The program has been arranged so that:

If outputs are also used as inputs (‘feedback loops’), the execution order can become complicated. In these cases, we advise that you use ClearSCADA's built-in diagnostics tool to check the execution order of your programs. The diagnostics tool shows the ST that ClearSCADA generates for your diagram, from which you can clearly see the execution order. If the order is not as you expected, you can alter your diagram as required. When you save the altered diagram, ClearSCADA will generate new ST for the program and you can use this to see how your changes have affected the execution order.

To run the diagnostics tool:

  1. Display a Logic Program in Design Mode.
  2. Select the Compile with Diagnostics from the Build command group on the Logic tab.

Example:

The following function block diagram is an example of a Logic program that could be used as a safety interlock for controlling a pump. It is used to control a pump - the pump cannot be started when there is no flow. This is achieved by establishing these relationships:

  • When a ‘StartPump’ signal is sent, the pump motor starts. However, if a flow has not been detected after a 120 second period, the pump is stopped and locked out (the pump stops responding to controls).
  • When a ‘StopPump’ signal is sent, the pump motor stops running.
  • When a ‘ResetPump’ signal is sent, the pump is no longer locked out. A ‘StartPump’ signal can be sent to the pump to attempt to start it, but if a flow is not detected within 120 seconds, the pump will be locked out again.

As you can see, the ‘LockedOut’ output is also used as an input for an AND function. This means there is a ‘feedback loop’.

Engineers can view the execution order by running the Compile with Diagnostics tool. This displays the function block diagram as ST code in the compiler, and lists the order in which the various elements of the program are executed.

The Compile with Diagnostics feature is selected and it shows the ST that ClearSCADA has generated for the Function Block Diagram. The execution order is clearly shown in the ST code, with the code being executed from top to bottom:

By analyzing the ST that has been generated for the Function Block Diagram, we can see that the execution order is as follows:

ClearSCADA executes the elements to produce the ‘LockedOut’ output/input first, and then executes the elements required to produce the ‘PointState’ output.


Disclaimer

ClearSCADA 2017 R3